Multi-channel memory architecture: Difference between revisions

Revision as of 20:01, 12 July 2005

Revision as of 05:23, 21 July 2005

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==Reason For Being==

[[Image:ram_bottleneck.gif|frame|Graphic illustrating bottleneck between CPU, RAM, and other peripherals]]

Dual channel technology was created to address the issue of bottlenecks. Increased processor speed and performance requires other, less prominent components are required to keep pace.

The most conspicuous of these parts is the memory controller, which regulates data flow between CPU and the system memory. The memory controller determines the types and speeds of RAM as well as the maximum size of each individual memory module and the overall memory capacity of the system. There are many memory controller designs; prior to 2003, the most common was the single channel configuration. Among its advantages are its low cost and flexibility. Its ability to produce a bottleneck effect arises when it is unable to keep up with the processor, leaving it with nothing to process while the memory controller is struggling to keep up with the data flow. Under the single channel architecture, any CPU with a bus speed that is greater than the memory speed would be liable to fall prey to this bottleneck effect.