Manycore processing unit: Difference between revisions

Revision as of 13:30, 11 March 2008

Revision as of 21:28, 11 March 2008

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A '''many-core processing unit''' (or MPU for short) is a type of [[microprocessor]] characterized by

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== History and evolution ==

=== Origins: network processing units (NPU) ===

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=== Integrated memory controllers ===

Performance of typical MPU applications, such as [[packet (information technology)|packet]] processing and [[network control protocols]] (e.g. [[Signalling (telecommunications)|signalling]] and [[call control]]), is often sensitive to first-access [[memory latency]], i.e. the time taken to access memory that is not [[Cache|cachedcache]]d on chip, owing to high cache miss rate. This is sometimes more important than peak [[memory bandwidth]]. To achieve low first-access latency MPUs have integrated [[memory controllers]]. This is distinct from [[Intel]] and [[IBM]] general purpose processors that use separate memory controller devices adjacent to the processors and are more optimized for maximum bulk memory throughput.

=== Integrated streaming packet IO hardware ===

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Many MPU applications can benefit from specialized hardware processing for [[Hardware acceleration|acceleration]] functions for common tasks in packet processing:

* [[Bandwidth management|traffic management]], such as [[Class of service]] [[Queue (data structure)|queues]] with [[Congestioncongestion control|congestion controls]]s like [[Tail drop|tail-drop]] and [[random early detection]]

* [[Scheduling algorithm]]s such as [[Priority queue|strict priority]] and [[weighted fair queueing]]

* [[Computer security|Security]] functions including: bulk encryption and decryption, random number generation, packet authentication hash computation

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== MPU applications ==

=== In telecommunications and networking equipment ===