Bit-serial architecture: Difference between revisions

Revision as of 04:27, 4 May 2008

Revision as of 17:38, 25 May 2008

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==Introduction==

In [[digital logic]] applications, Bit-Serial architectures are direct contrast to [[Bit-Parallel]] where a data word tends to be a one to one function of the system clock signal. A Bit-Serial architecture processes a data word as a function of the [[system clock signal]] multiplied by the length of the data word. Hence, only one bit of data is processed in a given component at a given point in time.

==References==