Architecture Design and Assessment System: Difference between revisions

Revision as of 07:38, 8 June 2008

Revision as of 20:53, 8 June 2008

Line 6:

{{simulation-software-stub}}

== Simulation Model ==

An ADAS model consisted of nodes connected by directed arcs.

For abstract simulation a node represents a [[process (systems engineering)]] in the system that you are modeling. The readiness for execution or firing of this process requires that: its inputs are satisfied, space is available for its outputs, and its shared resource/hardware is available. During execution the node consumes its inputs, uses the resource for the prescribed duration, then produces its outputs.

The inputs and outputs of a process are represented by discrete tokens. These tokens flow along the arcs in the graph. If the maximum arc size is greater that one, then an arc would respresent a buffer between system processes.

The refine the model of the system, a subgraph could be placed below the node to refine the behavior of that process.

Physical and behavioral properties were attached to nodes and arcs in the form of attributes. The attribute definition language allowed the computation of attributes from ancestor attributes and global values.

== References ==

Line 13 ⟶ 25:

</div>

== ExternalFurther linksReading ==

* [http://portal.acm.org/citation.cfm?id=317825.317921 An Architecture Design and Assessment System for Software/Hardware Codesign, Proceedings of the 22nd ACM/IEEE conference on Design automation, 1985]

Line 39 ⟶ 51:

* The Practice of Prolog: a Prolog-based VLSI editor, Leon Sterling, 1990, ISBN 0262193019

* [http://ieeexplore.ieee.org/Xplore/login.jsp?url=/iel2/640/5940/00230671.pdf?tp=&isnumber=&arnumber=230671 Design Automation Technology for Codesign: Status and Directions,1992 IEEE International Symposium on Circuits and Systems]

* [http://ieeexplore.ieee.org/Xplore/login.jsp?url=/iel2/566/4267/00165823.pdf?arnumber=165823 Aladdin Software Support, Proceedings of the IEEE 1991 National Aerospace and Electronics Conference]

* Performance Analysis of a Large-Grain Dataflow Scheduling Paradigm, NASA Langley, June 1993, page 8 http://ntrs.nasa.gov/archive/nasa/casi.ntrs.nasa.gov/19930023024_1993023024.pdf

* [http://ieeexplore.ieee.org/Xplore/login.jsp?url=/iel2/168/3349/00111315.pdf?arnumber=111315 Automated Fault Tolerance Evaluator for System Design, Simulation, and Analysis, Proceedings., IEEE/AIAA/NASA 9th Digital Avionics Systems Conference, 1990]

* Virtual Prototyping, Digital Signal Processing Systems, 1998 Lockheed Martin Technology Symposium, slide 7 http://www.atl.lmco.com/projects/csim/vp4C.pdf

[[Category:Computer-aided design software]]