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== Debug using DFT features ==
In addition to being useful for manufacturing "go/no go" testing, scan chains can also be used to "debug" chip designs. In this context, the chip is exercised in normal "functional mode" (for example, a computer or mobile-phone chip might execute assembly language instructions). At any time, the chip clock can be stopped, and the chip re-configured into "test mode". At this point the full internal state can dumped out, or set to any desired values, by use of the scan chains. Another use of scan to aid debug consists of scanning in an initial state to all memory elements and then go back to functional mode to perform system debug. The advantage is to bring the system to a known state without going through many clock cycles. This use of scan chains, along with the clock control circuits are a related sub-discipline of logic design called "Design for Debug" or "Design for Debugability".
<ref>
[http://www.edn.com/article/CA6451246.html?nid=3673 "Design for debugging: the unspoken imperative in chip design"]
article by Ron Wilson, EDN, 6/21/2007
</ref>
== See also ==
* [[JTAG]]
* [[Automatic test equipment]]
* [[Automatic test pattern generation]]
* [[BIST]]
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== References ==
''Electronic Design Automation For Integrated Circuits Handbook'', by Lavagno, Martin and Scheffer, ISBN 0-8493-3096-3 A survey of the field of [[electronic design automation]]. This summary was derived (with permission) from Vol I, Chapter 21, ''Design For Test'', by Bernd Koenemann.
<references />
[[Category:Electronic design automation]]
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