Flow to HDL: Difference between revisions

Revision as of 06:59, 26 November 2007

Revision as of 00:29, 2 September 2008

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This page is to describe tools and methods that convert Flow based system design into hardware description languages like [[VHDL]] or [[Verilog]]. Typically this is a method of creating designs for [[Field-programmable_gate_arrayprogrammable gate array]], [[ASIC]] prototyping and [[DSP]] design. Flow based system design is well suited to [[Field-programmable_gate_arrayprogrammable gate array|FPGA]] design as it's easier to specify the innate parallelism of the architecture.

== History==

The use of flow-based design tool in engineering is a reasonably new trend, most widely used example is [[Unified Modeling Language|UML]] for software design. The use of flow based design tools creates in theory allows for more holistic system design and faster development. There are other tools and flow that aim to achieve the same but with [[C_programming_languageC programming language|C]] or C like languages, these are discussed in the [[C_to_HDLC to HDL]] page.

== Applications ==

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*[http://www.cse.clrc.ac.uk/disco/publications/FPGA_overview_2.0.pdf] an overview of flows by Daresbury Labs.

*[http://www.xilinx.com/products/design_tools/logic_design/advanced/esl/index.htm] Xilinx's ESL initiative, some products listed and C to VHDL tools.

[[Category:Electronic design]]