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*The level of effort required to debug and then verify the design is proportional to the maturity of the design. That is, early in the design’s life, bugs and incorrect behavior are usually found quickly. As the design matures, it takes longer to find the errors. This is beneficial early in the design process. It becomes more problematic later.
*Simulation is completely general. Any hardware design can be simulated. The only limits are time and computer resources.
Prospective way to accelerate logic simulation is using distributed and parallel computations. <ref> Software system for distributed event-driven logic simulation. Ladyzhensky Y.V., Popoff Y.V. Proceedings of IEEE East-West Design & Test Workshop(EWDTW'05). IEEE EWDTW, 2005, p.119-122 ISBN 966-659-113-8 </ref>
== Limitations of logic simulation ==
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