Hardware verification language: Difference between revisions

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Revision as of 10:03, 14 November 2008

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A '''Hardware Verification Language''', or '''HVL''', is a programming language used to verify the designs of [[electronic circuits]] written in a [[hardware description language]]. HVLs typically include features of a [[high-level programming language]] like [[C++]] or [[Java (programming language)|Java]] as well as features for easy bit-level manipulation similar to those found in [[hardware description language|HDLs]].

[[OpenVera]], [[Specman|Specmane (verification language)|e]], and [[SystemC]] are the most commonly used HVLs, while [[SystemVerilog]] attempts to combine HDL and HVL constructs into a single standard.

== See also ==

*[[OpenVera]]

*[[e (verification language)|e]]

*[[Specman]]

*[[SystemC]]

*[[SystemVerilog]]