Property Specification Language: Difference between revisions

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'''Property Specification Language''' is a language [[standard]]ized by [[Accellera]] for specifying [[Property (philosophy)|properties]] or [[assertion (computing)|assertions]] about [[hardware]] designs. The properties can then be [[simulation|simulated]] or [[Formal verification|formally verified]]. It comes in two flavors, one for [[VHDL]] and one for [[Verilog]].

'''Property Specification Language''' is a language [[standard]]izeddeveloped by [[Accellera]] for specifying [[Property (philosophy)|properties]] or [[assertion (computing)|assertions]] about [[hardware]] designs. The properties can then beSince [[simulation|simulatedSeptember]] or [[Formal2004]] verification|formallythe verified[[standard]].ization Iton comesthe inlanguage twohas flavors,been onedone forin [[VHDLIEEE]] and1850 oneworking forgroup. The properties can then be [[Verilogsimulation|simulated]] or [[Formal verification|formally verified]].

More information is available at

Propery Specification Language aims to be used with multiple electronic system design languages such as

* [[VHDL]] (IEEE 1076),

* [[Verilog]] (IEEE 1364),

* [[System Verilog]] (IEEE 1800), and

* [[SystemC]] by [[OSCI]].

== See also ==

* [http://www.eda.org/ieee-1850 IEEE 1850 working group]

* [http://www.accellera.org/ Accellera]

* [http://www.pslsugar.org/ The PSL/Sugar Consortium]

* [http://www.doulos.com/knowhow/psl/ Designers guide to PSL]

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[[Category: Hardware description languages]]

[[Category: Electronic Design Automation]]