Bit-serial architecture: Difference between revisions

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=Bit-Serial Digital Architecture=

In [[digital logic]] applications, '''Bit-Serial''' architectures are direct contrastcontrasted to [[Parallel transmission|Bit-Parallel]] where a [[data word]] tends to be a [[one -to -one function]] of the [[system clock]] signal. A Bit-Serial architecture processes a data word as a function of the [[system [[clock signal]] multiplied by the length of the data word. Hence, only one bit of data is processed in a given component at a given point in time.

==Introduction==

In [[digital logic]] applications, Bit-Serial architectures are direct contrast to [[Bit-Parallel]] where a data word tends to be a one to one function of the system clock signal. A Bit-Serial architecture processes a data word as a function of the [[system clock signal]] multiplied by the length of the data word. Hence, only one bit of data is processed in a given component at a given point in time.

==References==

*[http://portal.acm.org/citation.cfm?id=503063 Application of [[FPGA]] technology to accelerate the [[finite-difference time-___domain]] (FDTD) method]

Below are referenced some examples of research making use of Bit-Serial endowed architectures.

*[http://portal.acm.org/citation.cfm?id=741014 BIT-Serial [[FIR Filtersfilter]]s with CSD Coefficients for FPGAs]

[http://portal.acm.org/citation.cfm?id=503063 Application of FPGA technology to accelerate the finite-difference time-___domain (FDTD) method]

[http://portal.acm.org/citation.cfm?id=741014 BIT-Serial FIR Filters with CSD Coefficients for FPGAs]