26-bit computing: Difference between revisions

Revision as of 00:39, 28 October 2005

Revision as of 14:21, 7 November 2005

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Despite being [[32-bit]] internally, processors prior to the ARM6 had only a '''26-bit PC and [[Address bus]]''', and were consequently limited to 64MB of adressable [[Random_Access_Memory|memory]]. This was still a vast amount of memory at the time, but because of this limitation, architectures since have included various steps away from the original 26-bit design.

The ARM6 introduced a '''32-bit PC''' and '''seperateseparate PSR''', as well as a '''32-bit address bus''', allowing 4GB of memory to be addressed. The change in the PC/PSR layout caused incompatibility with code written for previous architectures, so the processor also included a 26-bit compatibility mode which used the old PC/PSR combination. The processor could still address 4GB in this mode, but could not [[Execution_(computers)|execute]] anything above address 3FFFFFC (64MB). This mode was used by [[RISCOS]] running on the [[Risc_PC|Acorn RiscPC]] to utilise the new processors while retaining compatibility with existing software.

More recent ARM architectures such as [[Intel]]'s [[XScale]] have dropped the 26-bit mode altogether.