Template:Infobox CPU architecture/doc: Difference between revisions

Revision as of 15:47, 10 May 2009

Revision as of 15:58, 10 May 2009

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<pre>

{{Infobox CPU architecture

| name = Name of architecture, e.g. x86, SPARC, PowerPC, MIPS, ARM

| designer = Designer of the architecture

| bus = Width of bus, e.g. 32-bit, 64-bit

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| endianness = Byte ordering, i.e. Little, Big, Bi

| extensions = ISA extensions, i.e. MMX, SSE, AltiVec, etc

| Openopen = Is the architecture open or not? (as in free or proprietary)

}}

</pre>

All fields are optional.

== Example ==

{{Infobox CPU architecture

| name = SPARC

| designer = [[Sun Microsystems]]

| bus = 64-bit (32 → 64)

| introduced = 1985

| version = V9

| design = RISC

| type = Register-Register

| encoding = Fixed

| branching = Condition code

| endianness = Bi (Big → Bi)

| extensions = [[Visual Instruction Set|VIS]] 1.0, 2.0, 3.0

| open = Yes

}}

<pre>

{{Infobox CPU architecture

| name = SPARC

| designer = [[Sun Microsystems]]

| bus = 64-bit (32 → 64)

| introduced = 1985

| version = V9

| design = RISC

| type = Register-Register

| encoding = Fixed

| branching = Condition code

| endianness = Bi (Big → Bi)

| extensions = [[Visual Instruction Set|VIS]] 1.0, 2.0, 3.0

| open = Yes

}}

</pre>

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