A Block diagram Language: Difference between revisions

Revision as of 09:44, 15 April 2009

Revision as of 04:04, 20 July 2009

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{{orphanArticle issues|dateorphan =December 2008|notability =August 2008|COI =July 2009}}

{{Notability|date=August 2008}}

'''A Block diagram Language (ABL)''' is the graphic companion language of the textual [[hardware description language]] [[KARL]], which supports [[Structured hardware design]]. It has been authored by [[Reiner Hartenstein]] and jointly implemented by the [[Xputer]] Lab at [[TU Kaiserslautern]] and Guglielmo Girardi at [[CSELT]], Torino, Italy, as the ABLED interactive graphic hardware design editor with automatic interconnect compatibility check. The [[Domino notation]] of ABL is based on structured wiring function primitives and topological notations of [[KARL]] and allows interactive interconnect synthesis by module block abutment. A couple of other design tools are based on these calculus-like notations, like ARIANNA (interactive chip floor plan generator, and GENMON from [[CSELT]]), the BACH compiler, an [[ASIC]] Data path module generator, and others.

{{COI}}

'''A Block diagram Language (ABL)''' is the graphic companion language of the textual [[hardware description language]] [[KARL]], which supports [[Structured hardware design]]. It has been authored by [[Reiner Hartenstein]] and jointly implemented by the [[Xputer]] Lab at [[TU Kaiserslautern]] and Guglielmo Girardi at [[CSELT]], Torino,Italy, as the ABLED interactive graphic hardware design editor with automatic interconnect compatibility check. The [[Domino notation]] of ABL is based on structured wiring function primitives and topological notations of [[KARL]] and allows interactive interconnect synthesis by module block abutment. A couple of other design tools are based on these calculus-like notations, like ARIANNA (interactive chip floor plan generator, and GENMON from [[CSELT]]), the BACH compiler, an [[ASIC]] Data path module generator, and others.

== Literature ==

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*V. G. Moshnyaga, H. Onodera, K. Tamaru, H. Yasuura: A Language for Designing Data-Path Module Generators; Int’l Design Workshop "Russian Workshop’92", Moscow, Russia, 1992

*V. G. Moshnyaga, H. Yasuura: A Language for Designing Module Generators; Proc. SASIMI’92 - Synthesis and Simulation Meeting and Int’l Exchange, Kobe, Japan, Apr. 1992

*M. Ayala-Rincon et al.: Modeling and prototyping dynamically reconfigurable systems for efficient computation of dynamic programming methods by rewriting-logic; Proceedings of the 17th symposium on Integrated circuits and system design 2004, Pernambuco, Brazil, September 077 - 11, 2004

*R. Hartenstein: Fundamentals of Structured Hardware Design - A Design Language Approach at Register Transfer Level; North Holland/American Elsevier Amsterdam/New York 1977

*R. Hartenstein: The History of KARL and ABL; in: J. Mermet (editor): Fundamentals and Standards in Hardware Description Languages; Kluwer Academic Publishers, September 1993

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* [http://xputers.informatik.uni-kl.de/karl/karl_history_fbi.html The History of KARL and ABL]

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[[Category:Hardware description languages]]

[[Category:Electronic design]]