Convex Computer: Difference between revisions

Revision as of 07:43, 30 August 2009

Revision as of 07:45, 30 August 2009

Line 8:

The '''C2''' was a crossbar-interconnected [[multiprocessor]] version of the C1, with up to four CPUs, released in 1988. It used newer 20,000-gate CMOS and 10,000-gate [[emitter-coupled logic]] (ECL) gate arrays for a boost in clock speed from 10 MHz to 25 MHz, and rated at 50 MFLOPS peak for double precision per CPU (100 MFLOPS peak for single precision). It was Convex's most successful product.

The '''C2''' was followed by the '''C3''' in 1991, being essentially similar to the C2 but with a faster clock and support for up to 8eight CPUs implemented with low -density GaAs FPGAs. Various configurations of the C3 were offered, with between 50 to 240 MFLOPS per CPU. However, the C3 and the Convex business model were overtaken by changes in the computer industry. The arrival of RISC Microprocessorsmicroprocessors meant that it was no longer possible to develop cost-effective high -performance computing as a standalone small low-volume company. While the C3 was delivered late, which resulted in lost sales, it was still not going to be able to compete with commodity high-performance computing in the long run.

Another speed boost was planned in the '''C4''', which moved the hardware implementation to [[GaAs]]-based chips, following an evolution identical to that of the Cray machines, but the effort was too little, too late. Some considered the whole C4 program to be nothing more than chasing a business in decline. By this time, even though Convex was the first vendor to ship a [[GaAs]] based product, they were losing money.