Talk:Synchronous dynamic random-access memory: Difference between revisions

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m moved Talk:SDRAM to Talk:Synchronous dynamic random access memory: All articles about memory spell out thew acronym
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:As you said, this talk page is for discussing the article. May I suggest posting your question at the [[WP:RD/C|computing reference desk]]? -- [[User:Matt Britt|mattb]] <code>@ 2007-04-14T00:04Z</code>
 
== 1st paragraph: asynchronous operated "as quickly as possible"? What about propagating delays? ==
 
The 1st paragraph indicates that asynchronous operated "as quickly as possible" because it doesn't have to wait for a clock signal. I could be wrong here (it's been 15 years since then when I jumped to the solar PV industry), but when I was a DRAM integration/yield engineer for Micron while we were migrating from asynchronous to synchronous I understood the asynchronous problem differently.
 
As I understood it, since asynchronous transistors were not tied to a clock then as data traveled between the data-pins and the cell ''each transistor's latching was controlled by the transistor in front of it, introducing nested propagation delays''.
 
Am I wrong? Wasn't synchronous intended to reduce propagation delays caused by this nested-transistor-operation in the periphery? If so then it seems this first paragraph should be changed from:
<blockquote>
Traditionally, dynamic random access memory ([[DRAM]]) has an asynchronous interface which means that it responds as quickly as possible to changes in control inputs. SDRAM has a synchronous interface, meaning that it waits for a [[clock signal]] before responding to control inputs and is therefore synchronized with the computer's system bus.
</blockquote>
 
to:
<blockquote>
Traditionally, dynamic random access memory ([[DRAM]]) has an asynchronous interface which means that data propagated through nested gates (transistors) to get the memory cell as quickly as the gates could propagate the data. SDRAM has a synchronous interface, meaning that these gates are synchronized with computer's system bus [[clock signal]], allowing timing optimization to reduce those propagation delays.
</blockquote>