Hardware verification language: Difference between revisions

Revision as of 12:46, 15 October 2009

Revision as of 12:47, 15 October 2009

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A '''Hardware Verification Language''', or '''HVL''', is a programming language used to verify the designs of [[electronic circuits]] written in a [[hardware description language]]. HVLs typically include features of a [[high-level programming language]] like [[C++]] or [[Java (programming language)|Java]] as well as features for easy bit-level manipulation similar to those found in [[hardware description language|HDLs]]. Many HVLs will provide constrained random stimulus generation, and functional coverage constructs to assist with complex hardware verification.

[[SystemVerilog]], [[OpenVera]], [[Specmane (verification language)|Specman e]], and [[SystemC]] are the most commonly used HVLs, while [[SystemVerilog]] attempts to combine HDL and HVL constructs into a single standard.<ref>

[http://theasicguy.com/2009/02/03/verification-methodology-poll/ The ASIC Guy Verification Poll]

</ref>

<ref>

[http://theasicguy.com/2009/01/27/dvcon-survey-results-what-do-they-mean/ DVCon Language Poll]

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[[SystemVerilog]] attempts to combine HDL and HVL constructs into a single standard.

== See also ==

*[[OpenVera]]

*[[e (verification language)|e]]

*[[Specman]]

*[[SystemC]]

*[[SystemVerilog]]

*[[Property Specification Language]]

== References ==

[[Category:Hardware Verification Languages| ]]

<references/>

== External links ==

Think Verification: http://www.thinkverification.com/

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[[Category:Hardware Verificationverification Languageslanguages| ]]

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