Hardware verification language: Difference between revisions

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A '''Hardware Verification Language''', or '''HVL''', is a programming language used to verify the designs of [[electronic circuits]] written in a [[hardware description language]]. HVLs typically include features of a [[high-level programming language]] like [[C++]] or [[Java (programming language)|Java]] as well as features for easy bit-level manipulation similar to those found in [[hardware description language|HDLs]]. Many HVLs will provide constrained random stimulus generation, and functional coverage constructs to assist with complex hardware verification.

[[SystemVerilog]], [[OpenVera]], [[e (verification language)|e]], and [[SystemC]] are the most commonly used HVLs,.<ref>[http://theasicguy.com/2009/02/03/verification-methodology-poll/ The ASIC Guy Verification Poll]</ref><ref>[http://theasicguy.com/2009/01/27/dvcon-survey-results-what-do-they-mean/ DVCon Language Poll]</ref> [[SystemVerilog]] attempts to combine HDL and HVL constructs into a single standard.

[http://theasicguy.com/2009/02/03/verification-methodology-poll/ The ASIC Guy Verification Poll]

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[http://theasicguy.com/2009/01/27/dvcon-survey-results-what-do-they-mean/ DVCon Language Poll]

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[[SystemVerilog]] attempts to combine HDL and HVL constructs into a single standard.

==See also==

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== References ==

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== External links ==