Placement (electronic design automation): Difference between revisions

Revision as of 21:54, 19 December 2005

Revision as of 22:09, 19 December 2005

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'''Placement''' is an essential step in [[electronic design automation]] - the portion of the physical design flow since itthat assigns exact locations for various circuit

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'''Placement''' is an essential step in the physical design flow since it assigns exact locations for various circuit

components within the chip’s core area. An inferior placement assignment will not only affect the

chip’s[[Integrated circuit | chip]]'s performance but might also make it nonmanufacturable by producing excessive wirelength, which

is beyond available [[Routing (EDA) | routing]] resources. Consequently, a placer must perform the assignment while optimizing

a number of objectives to ensure that a circuit meets its performance demands. Typical placement

objectives include

*Total wirelength: Minimizing the total wirelength, or justthe wirelengthsum of the length of all the wires in the design, is the primary objective of most existing placers. This not only helps minimize chip size, and hence cost, but also minimizes power and delay, which are proportional to the wirelength and wirelength square, respectively.

*Timing: The [[Clock signal | clock]] cycle of a chip is determined by the delay of its longest path, usually referred to as the critical path. Given a performance specification, a placer must ensure that no path exists with delay exceeding the maximum specified delay.

*Congestion: While it is necessary to minimize the total wirelength to meet the total routing resources, it is also necessary to meet the routing resources within various local regions of the chip’s core area. A congested region might lead to excessive routing detours.

*Power: Power minimization typically involves distributing the locations of cell components so as to reduce the overall power consumption, alleviate hot spots, and smooth temperature gradients.

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===Placement within the EDA design flow===

A placer takes a given synthesized

circuit [[netlist]] together with a technology library and produces a valid placement layout. The layout

is optimized according to the aforementioned objectives and ready for cell resizing and buffering — a step

essential for timing and signal integrity satisfaction. Clock-tree synthesis and [[Routing (EDA) | routing]] follow, completing

the physical design process. In many cases, parts of, or the entire, physical design flow are iterated a number

of times until closure is achieved.

In the case of [[application -specific integrated circuitscircuit]]s, or (ASIC)ASICs, the chip’s core layout area is comprised of a

number of fixed height rows, with either some or no space between them. Each row consists of a number

of sites which can be occupied by the circuit components. A free site is a site that is not occupied by any component. Circuit components are either standard cells, macro blocks, or I/O pads. Standard cells have a

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what is commonly referred to as mixed-mode placement.

In addition to ASICs, placement retains its prime importance in gate array structures such as [[field -programmable gate arraysarray]]s (FPGAs). In FPGAs, placement maps the circuit’s subcircuits into programmable FPGA logic blocks in a manner that guarantees the completion of the subsequent stage of routing.

== Basic techniques ==