Content deleted Content added
LouScheffer (talk | contribs) Add test compression |
→Scan design: mention SVF interchange format |
||
Line 36:
Straightfoward application of scan techniques can result in large vector sets with corresponding long tester time and memory requirements. [[Test compression]] techniques address this problem, by decompressing the scan input on chip and compressing the test output. Large gains are possible since any particular test vector usually only needs to set and/or examine a small fraction of the scan chain bits.
The output of a scan design may be provided in forms such as [[Serial Vector Format]] (SVF), to be executed by test equipment.
== Debug using DFT features ==
| |||