Template:Infobox CPU architecture/doc: Difference between revisions

Revision as of 01:40, 3 October 2009

Revision as of 15:30, 29 October 2009

Line 16:

| branching =

| endianness =

| page size =

| extensions =

| open =

| registers =

| gpr =

| fpr =

}}

</pre>

Line 37 ⟶ 39:

| branching = Branching evaluation, e.g. Condition register, Condition code, Compare and branch

| endianness = Byte ordering, i.e. Little, Big, Bi

| page size = Primary size of page, i.e. 4 KiB, 2 MiB, 1 GiB; does not include "huge pages" and other extensions

| extensions = ISA extensions, i.e. MMX, SSE, AltiVec, etc

| open = Is the architecture open or not? (as in free or proprietary)

Line 58 ⟶ 62:

| branching = Condition code

| endianness = Bi (Big → Bi)

| page size = 8 KiB

| extensions = [[Visual Instruction Set|VIS]] 1.0, 2.0, 3.0

| open = Yes

Line 75 ⟶ 81:

| branching = Condition code

| endianness = Bi (Big → Bi)

| page size = 8 KiB

| extensions = [[Visual Instruction Set|VIS]] 1.0, 2.0, 3.0

| open = Yes

Line 94 ⟶ 102:

; branching: Branching evaluation, e.g. Condition register, Condition code, Compare and branch

; endianness: Byte ordering, i.e. Little, Big, Bi

; page size: Primary size of page, i.e. 4 KiB, 2 MiB, 1 GiB; does not include "huge pages" and other extensions

; extensions: ISA extensions, i.e. MMX, SSE, AltiVec, etc

; open: Is the architecture open or not? (as in free or proprietary)