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{{Userspace draft|date=November 2009}}
'''Hybrid-core''' computing is the technique of extending a commodity [[instruction set architecture]] (e.g. [[x86]]) with application-specific instructions to accelerate application performance. It is a form of [[heterogeneous computing]]<ref>Heterogeneous Processing: a Strategy for Augmenting Moore's Law". Linux Journal 1/2/2006. http://www.linuxjournal.com/article/8368</ref> wherein multiple computational units (i.e. graphics processing unit (GPU)), custom acceleration logic (application-specific integrated circuit ([[ASIC]]) or reconfigurable field-programmable gate array ([[FPGA]])) coexist with a "commodity" processor.
Hybrid-core processing differs from general heterogeneous computing in that the computational units share a common logical address space, are cache coherent and an executable is composed of a single instruction stream—in essence a contemporary [[coprocessor]]. The instruction set of a hybrid-core computing system contains instructions that can be dispatched either to the host instruction set or to the application-specific hardware.
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