Multi-core processor: Difference between revisions

Revision as of 21:59, 22 December 2005

Revision as of 22:05, 22 December 2005

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[[Image:Dual Core Generic.png|thumb|190px|Conceptual diagram of a dual-core CPU, with CPU-local Level 1 caches, and shared, on-chip Level 2 caches.]]

Dual-core CPU technology first became a practical viability in [[2001]]{{ref|DSP}} as 180-[[nanometre|nm]] [[CMOS]] process technology became feasible for volume production. At this size, multiple copies of the largest microprocessor architectures could be incorporated onto a single production die. (Alternative uses of this newly available "real estate" include widening the bus and internal registers of existing CPU cores, or incorporating more high-speed cache memory on-chip.)

Multi-core microprocessors first became viable around the year 2000, as 180-[[nanometre|nm]] [[CMOS]] processes became feasible for volume production. {{ref|DSP}} At this gate size, multiple copies of large and complex CPU implementations could be incorporated onto a single production die. The first commercial example of a multi-core microelectronic CPU was [[IBM]]'s [[POWER4]], released in 2001. <!-- Need to check whether or not this is true -->

==Commercial examples==