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== History ==
Inspired by TRS <ref name="hoe1">[http://www.ece.cmu.edu/~jhoe/distribution/2000/iccad00.pdf Synthesis of Operation-Centric Hardware Descriptions].
James C. Hoe and Arvind. International Conference on Computer Aided Design (ICCAD), November 2000. and [[Bluespec]], Atom compiled circuit descriptions based on guarded atomic operations, or [[Term_Rewriting_System| conditional term rewriting]], into [[Verilog]] [[netlist|netlists]] for simulation and [[logic synthesis]].
As a hardware compiler, Atom's primary objective was to maximize the number of operations, or rules, that could execute in a given clock cycle without violating the semantics of atomic operations.
Based on the properties of conflict-free and sequentially-composable rules<ref name="hoe1"/>, Atom's author reduced maximizing execution concurrency to a [[feedback arc set]] optimization of a rule-data dependency graph --
an algorithm which is very similar, if not equivalent to James Hoe's original algorithm<ref name="hoe1" />.
For effective
== Overview ==
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