Computing with memory: Difference between revisions

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{{Userspace draft|source=ArticleWizard|date=March 2010}}

'''Computing with Memory''' refers to computing platforms where function response is stored in memory array, either one or two-dimensional, in the form of lookup tables (LUTs) and functions are evaluated by retrieving the values from the LUTs. These computing platforms can follow either a purely spatial computing model, as in '''''[[Field-programmable Programmablegate Gate Arraysarray]]''''' (FPGAsFPGA), or a temporal computing model, where a function is evaluated across multiple clock cycles. The latter approach aims at reducing the overhead of programmable interconnect in FPGA by folding interconnect resources inside a computing element. It uses dense two-dimensional memory arrays to store large multiple-input multiple-output LUTs. '''''Computing with Memory''''' differs from '''''Computing in Memory''''' or [[Processor-in-memory]] (PIM) concepts, widely investigated in the context of integrating a processor and memory on the same chip to reduce the memory bandwidth and latency. These architectures seek to reduce the distance the data travels between the processor and the memory. Berkeley IRAM project is one notable contribution in the area of PIM architectures.

[[Image:MCBMemory Logic Block.png|thumb|right|alt=Time-multiplexed execution of mapped application using embedded memory blocks .|Functional block diagram of Memory Based Computation.]]

Computing with memory platforms are typically used to provide the benefit of hardware reconfigurabilty. Reconfigurable computing platforms offer advantages in terms of reduced design cost, early time-to-market, rapid prototyping and easily customizable hardware systems. FPGAs present a popular reconfigurable computing platform for implementing digital circuits. They follow a purely spatial computing model. Since their inception in 1985, the basic structure of the FPGAs has continued to consist of two-dimensional array of Configurable Logic blocks (CLBs) and a programmable interconnect matrix <ref name="Ref 1" group="Ref"/>. FPGA performance and power dissipation is largely dominated by the elaborate programmable interconnect (PI) architecture <ref name="Ref 2" group="Ref"/><ref name="Ref 3" group="Ref"/>. An effective way of reducing the impact of the PI architecture in FPGA is to place small LUTs in close proximity (referred as '''''clusters''''') and to allow intra-cluster communication using local interconnects. Due to the benefits of a clustered FPGA architecture, major FPGA vendors have incorporated it in their commercial products such <ref name="Ref 4" group="Ref"/><ref name="Ref 5" group="Ref"/>. Investigations have also been made to reduce the overhead due to PI in fine-grained FPGAs by mapping larger multi-input multi-output LUTs to embedded memory blocks. Although it follows a similar spatial computing model, part of the logic functions are implemented using embedded memory blocks while the remaining part is realized using smaller LUTs <ref name="Ref 6" group="Ref"/>. Such a heterogeneous mapping can improve the area and performance by reducing the contribution of programmable interconnects.