Computing with memory: Difference between revisions

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Computing with memory platforms are typically used to provide the benefit of hardware reconfigurabilty. Reconfigurable computing platforms offer advantages in terms of reduced design cost, early time-to-market, rapid prototyping and easily customizable hardware systems. FPGAs present a popular reconfigurable computing platform for implementing digital circuits. They follow a purely spatial computing model. Since their inception in 1985, the basic structure of the FPGAs has continued to consist of two-dimensional array of Configurable Logic blocks (CLBs) and a programmable interconnect matrix <ref name="Ref 1" group="Ref"/>. FPGA performance and power dissipation is largely dominated by the elaborate programmable interconnect (PI) architecture <ref name="Ref 2" group="Ref"/><ref name="Ref 3" group="Ref"/>. An effective way of reducing the impact of the PI architecture in FPGA is to place small LUTs in close proximity (referred as '''''clusters''''') and to allow intra-cluster communication using local interconnects. Due to the benefits of a clustered FPGA architecture, major FPGA vendors have incorporated it in their commercial products <ref name="Ref 4" group="Ref"/><ref name="Ref 5" group="Ref"/>. Investigations have also been made to reduce the overhead due to PI in fine-grained FPGAs by mapping larger multi-input multi-output LUTs to embedded memory blocks. Although it follows a similar spatial computing model, part of the logic functions are implemented using embedded memory blocks while the remaining part is realized using smaller LUTs <ref name="Ref 6" group="Ref"/>. Such a heterogeneous mapping can improve the area and performance by reducing the contribution of programmable interconnects.

Contrary to the purely spatial computing model of FPGA, a reconfigurable computing platform that employs a temporal computing model (or a combination of both temporal and spatial) has also been investigated <ref name="Ref 7" group="Ref"/><ref name="Ref 8" group="Ref"/> in the context of improving performance and energy over conventional FPGA. These platforms, referred as '''''Memory Based Computing (MBC)''''', use dense two-dimensional memory array to store the LUTs. Such frameworks rely on breaking a complex function (''f'') into small sub-functions; representing the sub-functions as into multi-input, multi-output LUTs in the memory array; and evaluating the function ''f'' over multiple cycles. MBC can leverage on the high density, low power and high performance advantages of nanoscale memory <ref name="Ref 8" group="Ref"/>. Fig[[:Image:Memory Logic Block.png]] 1 shows the high-level block diagram of MBC. Each computing element incorporates a two-dimensional memory array for storing LUTs, a small controller for sequencing evaluation of sub-functions and a set of temporary registers to hold the intermediate outputs from individual partitions. A fast, local routing framework inside each computing block generates the address for LUT access. Multiple such computing elements can be spatially connected using FPGA-like programmable interconnect architecture to enable mapping of large functions. The local time-multiplexed execution inside the computing elements can drastically reduce the requirement of programmable interconnects leading to large improvement in energy-delay product and better scalability of performance across technology generations. The memory array inside each computing element can be realized by [[Content-addressable memory]] (CAM) to drastically reduce the memory requirement for certain applications <ref name="Ref 7" group="Ref"/>.

== References ==