Application-specific instruction set processor: Difference between revisions

Revision as of 10:18, 18 March 2010

Revision as of 14:03, 30 March 2010

Line 20:

[[it:Application-specific instruction-set processor]]

[[ru:ASIP]]

Increasing Design Costs

Designing an integrated circuit is getting increasingly expensive with each succeeding generation. Design difficulties arise from four distinct causes:

Deep-Submicron Effects (DSM):

The primary change is the increase in interconnect delay as a fraction of

the gate delay due to scaling effects. Since this is not available till physical design is over, the traditional synthesis flow of logic synthesis, with simple interconnect wire-load models, followed by physical synthesis does not work anymore.

Increased Complexity: The flip-side of smaller geometries is that we can

now integrate more transistors on the same die. This is amplified by the fact that manufacturing advances have further increased possible die-sizes.

Heterogeneous Integration: Increased functionality of systems at lower costs requires the integration of heterogeneous functionality on the same die. In addition to the traditional digital part, it is not uncommon to integrate analog and mixed signal components on the same die.

Shrinking Time-to-Market: : While the above three factors arise out of technology challenges, the fourth arises from commercial challenges. Increasingly, the time-to-market for products is shrinking – providing the added degree of difficulty in realizing commercially successful designs.

Increasing Manufacturing Costs

Mask costs for designs in today’s 180-130nm technologies are in the 0.5-1M$ range.

Testing 100M-1B transistor circuits at high operating frequencies poses significant challenges.

ITRS 2001 states that “test costs have grown exponentially compared to manufacturing costs".