Programmable interrupt controller: Difference between revisions

Revision as of 00:34, 1 April 2010

Revision as of 23:12, 7 July 2010

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In [[computing]], a '''programmable interrupt controller''' ('''PIC''') is a device that is used to combine several sources of [[interrupt]] onto one or more [[CPU]] lines, while allowing priority levels to be assigned to its interrupt outputs. When the device has multiple interrupt outputs to assert, it will assert them in the order of their relative priority. Common modes of a PIC include hard priorities, rotating priorities, and cascading priorities. PICs often allow the cascading of their outputs to inputs between each other.

== Common features ==

PICs typically have a common set of registers: Interrupt Request Register (IRR), In-Service Register (ISR), Interrupt Mask Register (IMR). The IRR specifies which interrupts are pending acknowledgement, and is typically a symbolic register which can not be directly accessed. The ISR register specifies which interrupts have been acknowledged, but are still waiting for an [[End_of_interruptEnd of interrupt|End Of Interrupt]] (EOI). The IMR specifies which interrupts are to be ignored and not acknowledged. A simple register schema such as this allows up to two distinct interrupt requests to be outstanding at one time, one waiting for acknowledgement, and one waiting for EOI.

There are a number of common priority schemas in PICs including hard priorities, specific priorities, and rotating priorities.

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There are a number of common ways of acknowledging an interrupt has completed when an EOI is issued. These include specifying which interrupt completed, using an implied interrupt which has completed (usually the highest priority pending in the ISR), and treating interrupt acknowledgement as the EOI.

== Well-known PICs ==

One of the best known PICs, the [[Intel 8259|8259A]], was included in the [[x86 architecture|x86]] PC. In modern times, this is not included as a separate chip in an x86 PC. Rather, its function is included as part of the motherboard's [[Southbridge (computing)|southbridge]] chipset. In other cases, it has been completely replaced by the newer [[Advanced Programmable Interrupt Controller]]s which support more interrupt outputs and more flexible priority schemas.

==More Informationinformation==

More information on the Intel APIC can be found in the ''IA-32 Intel Architecture Software Developer's Manual, Volume 3A: System Programming Guide, Part 1, Chapter 10'', freely available on the [[Intel]] website.