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==Technical information==
The PPU is controlled via eight [[Processor register|registers]] visible in the [[CPU]]'s address space in the addresses $2000 through $2007. All data and information is passed to the PPU through these, except the raw tile data (there are exceptions, as some games had RAM instead of ROM to store the tile data, and the tiles had to be written each time), which is hardwired to the PPU's address space. The PPU uses the tile graphics data together with information stored by the program in the PPU's RAM, such as color and position, to render the final graphical output to the screen.
The lowest graphical components the PPU operates with are [[tile]]s, which are blocks of 8×8 or 8×16 pixels. The tiles are stored in a [[Read-only memory|ROM]] chip on the game cartridge. The tiles are the basic building blocks, used to create larger moving objects, or large static backgrounds.
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