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'''Fractional lambda switching''' (FλS) <ref>
| last1 = Baldi | first1 = M.
| authorlink1 = http://www.mario-baldi.net
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| url = http://staff.polito.it/mario.baldi/publications/TSMS2004_FLS.pdf
| format = [[Portable Document Format|PDF]]
| year = 2004 }}
In FλS, likewise in TDS, all packets in the same time frame are switched in the same way. Consequently, header processing is not required, which results in low complexity (hence high scalability) and enables optical implementation <ref>
</ref>
Scheduling through a switching fabric is based on a pre-defined schedule, which enables the implementation of a simple controller. Moreover, low-complexity switching fabric architectures, such as Banyan, can be deployed notwithstanding their blocking features, thus further enhancing scalability. In fact, blocking can be avoided during schedule computation by avoiding conflicting input/output connections during the same TF. Several results show that (especially if multiple wavelength division multiplexing channels are deployed on optical links between fractional λ switches) high link utilization can be achieved with negligible blocking using a Banyan network without speedup <ref>
| last1 = Baldi | first1 = M.
| authorlink1 = http://www.mario-baldi.net
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| url = http://staff.polito.it/mario.baldi/publications/TSMS2004_FLS.pdf
| format = [[Portable Document Format|PDF]]
| year = 2004 }}
</ref>.
Various aspects of the technology are covered by [http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=0&f=S&l=50&TERM1=synchrodyne&FIELD1=ASNM&co1=AND&TERM2=&FIELD2=&d=PTXT several patents] issued by both the [[United States Patent and Trademark Office]] and the [[European Patent Office]].{{
== References ==
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{{DEFAULTSORT:Fractional Lambda Switching}}
[[Category:Computer networking]]
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