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In the [[electronic design automation|automated]] design of [[integrated circuit]]s, '''signoff''' (also written as '''sign-off''') checks is the collective name given to a series of verification steps that must pass before the design can be [[tapeout|taped out]]. This implies an iterative process involving incremental fixes across the board in one or more check type and retesting the design.
== Check types ==
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* DRC/LVS - [http://www.mentor.com/products/ic_nanometer_design/verification-signoff/physical-verification/ Mentor Calibre], [http://www.magma-da.com/products-solutions/verification/quartzDRCLVS.aspx Magma Quartz], [http://www.synopsys.com/tools/implementation/physicalverification/pages/hercules.aspx Synopsys Hercules], [http://www.cadence.com/products/mfg/apv/pages/default.aspx Cadence Assura]
* Voltage drop analysis - [http://www.apache-da.com/apache-da/Home/ProductsandSolutions/SoCPowerNoiseReliability.html Apache Redhawk], [http://www.magma-da.com/products-solutions/lowpower/QuartzRail.aspx Magma Quartz Rail]
* Signal integrity analysis - [http://w2.cadence.com/datasheets/3073E_CeltIC_DS_Fnl.pdf Cadence CeltIC] (crosstalk noise), [http://www.synopsys.com/Tools/Implementation/SignOff/Pages/PrimeTime.aspx Synopsys PrimeTime SI] (crosstalk delay/noise), [http://www.extreme-da.com/Gold_Time_Suite.html Extreme-DA GoldTime SI] (crosstalk delay/noise)
* Static timing analysis - [http://www.synopsys.com/Tools/Implementation/SignOff/Pages/PrimeTime.aspx Synopsys PrimeTime], [http://www.magma-da.com/products-solutions/verification/quartzssta.aspx Magma Quartz SSTA], [http://www.cadence.com/products/di/ets/pages/default.aspx Cadence ETS], [http://www.extreme-da.com/Gold_Time_Suite.html Extreme-DA GoldTime]
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