System bus model: Difference between revisions

Revision as of 10:45, 18 May 2011

Revision as of 22:45, 20 May 2011

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{{Orphan|date=February 2009}}

{{merge to|Von Neumann architecture|discuss=Talk:System bus model#PROD|date=October 2010}}

[[Image:SystembusmodelComputer system bus.png|thumb|right|400px]]

The '''system bus model''' is a streamlined version of the [[Von Neumann architecture|von Neumann model]] of computer architecture.<ref>{{cite book |title=The essentials of computer organization and architecture |author1=Linda Null |author2=Julia Lobur |publisher=Jones & Bartlett Learning |year=2006 |isbn=9780763737696 |edition=2}}</ref> Its main feature is that it interconnects the processor, memory, and I/O subsystems by a single [[bus (computing)|bus]], divided in 3 components: [[data bus]], [[address bus]], [[control bus]].<ref name="POCA"/> Contemporary computer systems use several buses for cost-performance tradeoff reasons.<ref name="Stallings2009">{{cite book|author=William Stallings|title=Computer organization and architecture: designing for performance|year=2009|publisher=Prentice Hall|isbn=9780136073734|pages=66 & 87-89|edition=8th}}</ref>