Revision as of 12:19, 14 June 2011 edit 134.191.232.68 (talk) →Cache coherency: new section ← Previous edit		Revision as of 12:21, 14 June 2011 edit undo SineBot (talk \| contribs) Bots 2,564,739 edits m Signing comment by 134.191.232.68 - "→Cache coherency: new section" Next edit →
Line 17: Current version says: "In x86 based systems, an IPI synchronizes the cache and memory management unit (MMU) between processors." I agree that IPI may be used on some systems for cache coherency, but x86 has (at least for several years) hardware cache coherency protocol (which is software-invisible and doesn't use IPI) <span style="font-size: smaller;" class="autosigned">— Preceding [[Wikipedia:Signatures\|unsigned]] comment added by [[Special:Contributions/134.191.232.68\|134.191.232.68]] ([[User talk:134.191.232.68\|talk]]) 12:19, 14 June 2011 (UTC)</span><!-- Template:UnsignedIP --> <!--Autosigned by SineBot-->

Talk:Inter-processor interrupt: Difference between revisions