Bit-serial architecture: Difference between revisions

Revision as of 03:46, 20 April 2009

Revision as of 23:48, 18 June 2011

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In [[digital logic]] applications, '''Bitbit-Serialserial architectures''' architectures are contrasted to [[Parallel transmission|Bitbit-Parallelparallel]], where a [[data word]] tends to be a [[one-to-one function]] of the [[system clock]] signal. A Bitbit-Serialserial architecture processes a data word as a function of the system [[clock signal]] multiplied by the length of the data word. Hence, only one bit of data is processed in a given component at a given point in time.

==References==

*[http://portal.acm.org/citation.cfm?id=503063 Application of [[FPGA]] technology to accelerate the [[finite-difference time-___domain]] (FDTD) method]

*[http://portal.acm.org/citation.cfm?id=741014 BIT-Serial [[FIR filter]]s with CSD Coefficients for FPGAs]