Logic simulation: Difference between revisions

Revision as of 16:24, 10 May 2011

Revision as of 13:27, 24 June 2011

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==Advantages of logic simulation ==

Simulation is the key activity in the design [[verification]] process. That is not to say that it is an ideal process. It has some very positive attributes:

*It is a natural way for the designer to get feedback about their design. Because it is just running a program – the design itself – the designer interacts with it using the vocabulary and abstractions of the design. There is no layer of translation to obscure the behavior of the design.

*The level of effort required to debug and then verify the design is proportional to the maturity of the design. That is, early in the design’s life, bugs and incorrect behavior are usually found quickly. As the design matures, it takes longer to find the errors. This is beneficial early in the design process. It becomes more problematic later.

*Simulation is completely general. Any hardware design can be simulated. The only limits are time and computer resources.

Prospective way to accelerate logic simulation is using [[distributed computing|distributed]] and [[parallel computationscomputation]]s. <ref> Software system for distributed [[event-driven]] logic simulation. Ladyzhensky Y.V., Popoff Y.V. Proceedings of IEEE East-West Design & Test Workshop(EWDTW'05). IEEE EWDTW, 2005, p.119-122 ISBN 966-659-113-8 </ref>

== Limitations of logic simulation ==