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[[Code coverage]], functional coverage and logic coverage tools have all been developed to help gauge the completeness of simulation testing. None are complete solutions, though they all help. Formal alternatives have been less successful. Just like in the general software world, where proving programs correct has proven intractable, formal methods for verifying hardware designs have still not proven general enough to replace simulation. That is not surprising, since it is the same problem.
The second drawback motivates most of the research and development in simulation. That is, simulation is always orders of magnitude slower than the system being simulated. If a hardware system runs at 1GHz, a simulation of that system might run at 10-1000 Hz, depending on the level of the simulation and the size of the system. That is a slowdown of from 10<sup>6</sup> to 10<sup>8</sup>! Consequently, many people have spent a lot of time and effort finding ways to speed up logic simulation. The straightforward approach is to emulate the circuits on [[FPGA]]. FPGAs are the fine-grain supercomputers, intentionally designed for logic simulation. The emulation is only 10 times slower than the circuit implemented in true silicon ([[ASIC]]). Though, a lot of information is lost from observation -- only external I/O is available.
== Event simulation versus cycle simulation ==
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