Field-effect transistor: Difference between revisions

Revision as of 16:31, 15 September 2011

Revision as of 16:35, 15 September 2011

Line 17:

<ref>http://commons.wikimedia.org/wiki/File:Basic_JFET.png</ref>

<ref>http://commons.wikimedia.org/wiki/File:Actual_JFET.png</ref>

FET terminals are:

#* SOURCE (S) : through which the majority carriers enter the channel.

Conventional current entering the channel at S is designated by IS.

#* DRAIN (D) : through which the majority carriers leave the channel.

Conventional current entering the channel at D is designated by ID.

Drain to Source voltage is VDS.

#* GATE (G) : is the common terminal for the other two regions surrounding the channel.

By applying voltage to G, we can control ID.

Conventional current entering the channel at G is designated by IG.