Static random-access memory: Difference between revisions

Revision as of 20:57, 29 October 2011

Revision as of 20:59, 29 October 2011

Line 43:

===Bus behavior===

A [[RAM memory]] with an access time of 70 ns will output valid data within 70 ns from the time that the address lines are valid. But the data will remain for a hold time as well (5-10 ns). Rise and fall times also influence valid timeslots with approximately ~5 ns. By reading the lower part of an address range bits in sequence (page cycle) one can read <!-- and write? --->with significantly shorter access time (30 ns).

<ref>{{cite web|title=Tentative Toshiba mos digital integrated circuit silicon gate cmos 4,194,304-word by 16-bit cmos pseudo static RAM|url=http://toshiba.com/taec/components/Datasheet/51WHM616AXBN.pdf|format=PDF}} 070731 toshiba.com</ref>

==Applications and uses==

===Characteristics===

SRAM is more expensive, but faster and significantly less power hungry (especially idle) than [[DRAM]]. It is therefore used where either bandwidth or low power, or both, are principal considerations. SRAM is also easier to control (interface to) and generally more truly ''random access'' than modern types of DRAM. Due to a more complex internal structure, SRAM is less dense than DRAM and is therefore not used for high-capacity, low-cost applications such as the main [[Computer memory|memory]] in [[personal computer]]s.

====Clock rate and power====

The [[Electric power|power]] consumption of SRAM varies widely depending on how frequently it is accessed; it '''can''' be as power-hungry as dynamic RAM, when used at high frequencies, and some [[integrated circuit|IC]]s can consume many [[watt]]s at full bandwidth. On the other hand, static RAM used at a somewhat slower pace, such as in applications with moderately clocked microprocessors, draws very little power and can have a nearly negligible power consumption when sitting idle &mdash; in the region of a few micro-watts.

Line 80 ⟶ 78:

====Hobbyists====

Hobbyists, specifically homebuilt processor enthusiasts,<ref>{{cite web|title=Homemade CPU|url=http://3.14.by/en/read/homemade-cpus}}</ref>, often prefer SRAM due to the ease of interfacing. It is much easier to work with than [[DRAM]] as there are no refresh cycles and the address and data buses are directly accessible rather than [[multiplexed]]. In addition to buses and power connections, SRAM usually requires only three controls: Chip Enable (CE), Write Enable (WE) and Output Enable (OE). In synchronous SRAM, Clock (CLK) is also included.{{Citation needed|date=November 2010}}

==Types of SRAM==

Line 107 ⟶ 105:

*[[DDR SRAM]] &mdash; Synchronous, single read/write port, double data rate I/O

*[[Quad Data Rate SRAM]] &mdash; Synchronous, separate read & write ports, quadruple data rate I/O

===By flip-flop type===

* Binary SRAM