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[[RAM]] with an access time of 70 ns will output valid data within 70 ns from the time that the address lines are valid. But the data will remain for a hold time as well (5-10 ns). Rise and fall times also influence valid timeslots with approximately ~5 ns. By reading the lower part of an address range bits in sequence (page cycle) one can read <!-- and write? --->with significantly shorter access time (30 ns).
<ref>{{cite web|title=Tentative Toshiba mos digital integrated circuit silicon gate cmos 4,194,304-word by 16-bit cmos pseudo static RAM|url=http://toshiba.com/taec/components/Datasheet/51WHM616AXBN.pdf|format=PDF}} 070731 toshiba.com</ref>
===Design of memory subsystems===
[[File:30102011328.jpg|thumb|left|Organization of a 64K X 8 memory module using 16K X 1 static memory chips.]]
==Applications and uses==
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