Static random-access memory: Difference between revisions

Revision as of 16:04, 31 October 2011

Revision as of 20:01, 1 November 2011

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==SRAM operation==

An SRAM cell has three different states. It can be in: ''standby'' (the circuit is idle), ''reading'' (the data has been requested) and ''writing'' (updating the contents). The SRAM to operate in read mode and write mode should have "readeabilityreadability" and "write stability" respectively. The three different states work as follows:

* '''Standby'''

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[[RAM]] with an access time of 70 ns will output valid data within 70 ns from the time that the address lines are valid. But the data will remain for a hold time as well (5-10 ns). Rise and fall times also influence valid timeslots with approximately ~5 ns. By reading the lower part of an address range bits in sequence (page cycle) one can read <!-- and write? --->with significantly shorter access time (30 ns).

<ref>{{cite web|title=Tentative Toshiba mos digital integrated circuit silicon gate cmos 4,194,304-word by 16-bit cmos pseudo static RAM|url=http://toshiba.com/taec/components/Datasheet/51WHM616AXBN.pdf|format=PDF}} 070731 toshiba.com</ref>

==Applications and uses==