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# The 26-pin GPIO connector is not assembled on the board. The end-user must purchase and solder a 13×2 [[pin header]] with 0.1-inch (2.54 mm) spacing. The pin header can be either a straight pin header, mounted on either the bottom or the top, (to connect to a [[daughterboard]]) or it can be a right-angle shrouded box connector for use with a ribbon cable. <ref name="hq-qa" />
# At the moment [[RISC OS]] (shared source) is not yet supported, as it lacks essential drivers.<ref name="osnews risc os" />
# On the model B beta boards, 128 MiB is
# Level 2 Cache is 128 KiB, used primarily by the GPU, not the CPU, per page 6 of the datasheet.
==Reception==
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