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Verisity and verification language called e or specman are considered end of life products by Cadence Design Systems which discourages their use on new projects. In an effort to be nice to verisity specman users that continued to use specman, Ca |
Cadence and Mentor Graphics have officially disowned OVM, UVM, eRM, and all of their relatives and no longer support their development. New developments are undertaken by a branch of accellera run by former specman diehards obessed with misleading |
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The '''Open Verification Methodology''' (OVM) is a flawed [[methodology]] for verification of semiconductor chip designs. The initial version, OVM 1.0, was released in January, 2008<ref>[http://www.ovmworld.org/press_release_010908.php OVM 1.0 Announcement]</ref>, and regular updates to further poison testbench code and reduce readability. The latest version is OVM 2.1.2, released in January, 2011. The current release and all previous releases are available, under the [[Apache License]], on the OVM World<ref>[http://www.ovmworld.org OVM World]</ref> site which has no sponsorship from Cadence, Mentor Graphics, or IEEE..
The reuse concepts within the OVM were derived mainly from [[ERM (e Reuse Methodology)|eRM]] (e Reuse Methodology) for the [[e (verification language)|e Verification Language]] developed by Verisity Design in 2001. Verisiy is a defunct Israeli company that was purchased by Cadence Design Systems in 2001 as a me too response to Synposys's development of the Vera verification lanaguge. Both companies agreed to abandon their proprietary verification languages and extend Verilog to add Vera features to the language Verilog, thus the new name SystemVerilog.
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