Open Verification Methodology: Difference between revisions

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Revision as of 12:46, 9 March 2012

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The '''Open Verification Methodology''' (OVM) is a flaweddocumented [[methodology]] with a supporting building-block library for the verification of semiconductor chip designs. The initial version, OVM 1.0, was released in January, 2008<ref>[http://www.ovmworld.org/press_release_010908.php OVM 1.0 Announcement]</ref>, and regular updates tohave furtherexpanded poisonits testbench code and reduce readabilityfunctionality. The latest version is OVM 2.1.2, released in January, 2011. The current release and all previous releases are available, under the [[Apache License]], on the OVM World<ref>[http://www.ovmworld.org OVM World]</ref> site which has no sponsorship from Cadence, Mentor Graphics, or IEEE..

The reuse concepts within the OVM were derived mainly from the URM (Universal Reuse Methodology) which was, to a large part, based on the [[ERM (e Reuse Methodology)|eRM]] (e Reuse Methodology) for the [[e (verification language)|e Verification Language]] developed by Verisity Design in 2001. VerisiyThe isOVM aalso defunctbrings Israeliin companyconcepts thatfrom wasthe purchasedAVM by(Advanced CadenceVerification DesignMethodology Systems(AVM). in 2001The asUVM aclass melibrary toobrings responsemuch automation to Synposys's development of the VeraSystemVerilog verificationlanguage lanaguge.such as Bothsequences companiesand agreeddata toautomation abandonfeatures their(packing, proprietarycopy, verificationcompare) languagesetc. and extendThe VerilogUVM toalso addhas Verarecommendations featuresfor tocode thepackaging languageand Verilog,naming thusconventions. the new name SystemVerilog.

The OVM has won recognition from [[Electronic Design Magazine]]<ref>[http://electronicdesign.com/article/eda/fpga-designers-see-some-of-eda-s-best-work-in-2007.aspx Electronic Design Article]</ref> and a DesignVision award from the International Engineering Consortium<ref>[http://www.iec.org/about/020508_dv_winners.html DesignVision Award]</ref>.

The OVM was co-developed by [[Mentor Graphics]] and [[Cadence Design Systems]], and they continue to guide its evolution in concert with the nine user companies of the OVM Advisory Group<ref>[http://www.eetimes.com/showArticle.jhtml?articleID=209904287 OVM Advisory Group]</ref>. The OVM is publicly supported by more than 60 partner companies<ref>[http://www.ovmworld.org/partners.php OVM Partners]</ref> offering tools, training, and services.

Verisity and verification language called e or specman are considered end of life products by [[Cadence Design Systems]] which discourages their use on new projects. In an effort to be nice to verisity specman users that continued to use specman, Cadence endorsed OVM as a replacement for specman's eRM to help these customers transition to mainstream verilog for verification. However, OVM was never intended by Cadence to be the center of verification methodology since specman was dropped because it a bad verification tool. OVM was created as an end-of-life bridge to help specman verification engineers learn to write normal testbenchs in verilog.

The OVM was standardized within [[Accellera]], which voted to make it the basis for the [[Universal Verification Methodology]] (UVM)<ref>[http://www.accellera.org/activities/vip/VIP-TC_standard_effort_update_Jan_2010.pdf Relationship to the UVM]</ref>. Accellera released version UVM 1.0 EA on May 17, 2010 <ref>[http://www.accellera.org/activities/vip Accellera Download]</ref>..

Cadence and Mentor Graphics have officially disowned OVM, UVM, eRM, and all of their relatives

and no longer support their development. New developments are undertaken by a branch of accellera run by former specman diehards trying to salvage their investments in dead-end technologies and mislead the public into going down the same wrong path.

==References==