Signoff (electronic design automation): Difference between revisions

Revision as of 02:48, 25 March 2011

Revision as of 16:08, 6 June 2012

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* [[Layout versus schematic|LVS]] - Also known as schematic verification, this is used to verify that the [[placement (electronic design automation)|placement]] and [[routing (electronic design automation)|routing]] of the [[standard cell]]s in the design has not altered the functionality of the constructed circuit.

* [[Formal verification]] - Here, the logical functionality of the post-[[Integrated circuit layout|layout]] netlist (including any layout-driven optimization) is verified against the pre-layout, post-[[logic synthesis|synthesis]] [[netlist]].

* [[Power network design (IC)|Voltage drop]] analysis - Also known as IR-drop analysis, this check verifies if the [[Power network design (IC)|power grid]] is strong enough to ensure that the [[VDDIC power supply pin|voltage]] representing the binary '''high''' value never dips lower than a set margin (below which the circuit will not function correctly or reliably) due to the combined switching of millions of transistors.

* [[Signal integrity]] analysis - Here, noise due to crosstalk and other issues is analyzed, and its effect on circuit functionality is checked to ensure that capacitive glitches are not large enough to cross the [[threshold voltage]] of gates along the data path.

* [[Static timing analysis]] (STA) - Slowly being superseded by [[statistical static timing analysis]] (SSTA), STA is used to verify if all the logic data paths in the design can work at the intended [[clock frequency]], especially under the effects of [[Process corners|on-chip variation]]. STA is run as a replacement for [[SPICE]], because SPICE simulation's runtime makes it infeasible for full-chip analysis modern designs.