Despite beinghaving a [[32-bit]] internallyALU and word-length, processors priorbased on ARM Architecture version to1 theand ARM62 had only a 26-bit PC and [[address bus]], and were consequently limited to 64 MB of addressable [[Random_Access_Memory|memory]]. This was still a vast amount of memory at the time, but because of this limitation, architectures since have included various steps away from the original 26-bit design.
The ARM6ARM Architecture version 3 introduced a 32-bit PC and separate PSR, as well as a 32-bit address bus, allowing 4 GB of memory to be addressed. The change in the PC/PSR layout caused incompatibility with code written for previous architectures, so the processor also included a 26-bit compatibility mode which used the old PC/PSR combination. The processor could still address 4 GB in this mode, but could not [[Execution_(computers)|execute]] anything above address 3FFFFFC (64 MB). This mode was used by [[RISC OS]] running on the [[Risc_PC|Acorn Risc PC]] to utilise the new processors while retaining compatibility with existing software.
ARM Architecture version 4 made the support of the 26-bit addressing modes optional, and ARM Architecture version 5 onwards has removed them entirely.
More recent ARM architectures such as [[Intel]]'s [[XScale]] have dropped the 26-bit mode altogether.
