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<ref name="Ref 8"> S. Paul, S. Chatterjee, S. Mukhopadhyay and S. Bhunia, "Nanoscale Reconfigurable Computing Using Non-Volatile 2-D STTRAM Array", International Conference on Nanotechnology, 2009.</ref> in the context of improving performance and energy over conventional FPGA. These platforms, referred as Memory Based Computing (MBC), use dense two-dimensional memory array to store the LUTs. Such frameworks rely on breaking a complex function (''f'') into small sub-functions; representing the sub-functions as into multi-input, multi-output LUTs in the memory array; and evaluating the function ''f'' over multiple cycles. MBC can leverage on the high density, low power and high performance advantages of nanoscale memory <ref name="Ref 8"/>. [[:Image:Memory Logic Block.png]] shows the high-level block diagram of MBC. Each computing element incorporates a two-dimensional memory array for storing LUTs, a small controller for sequencing evaluation of sub-functions and a set of temporary registers to hold the intermediate outputs from individual partitions. A fast, local routing framework inside each computing block generates the address for LUT access. Multiple such computing elements can be spatially connected using FPGA-like programmable interconnect architecture to enable mapping of large functions. The local time-multiplexed execution inside the computing elements can drastically reduce the requirement of programmable interconnects leading to large improvement in energy-delay product and better scalability of performance across technology generations. The memory array inside each computing element can be realized by [[Content-addressable memory]] (CAM) to drastically reduce the memory requirement for certain applications <ref name="Ref 7"/>.
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* [[Reconfigurable Computing]]
* [[Field-programmable gate array]] (FPGA)
* [[Processor-in-memory]] (PIM)
* [[Computational RAM]]
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▲== References ==
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[[Category:Computer engineering]]
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