No instruction set computing: Difference between revisions

Revision as of 11:01, 29 August 2012

Revision as of 18:43, 10 October 2012

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== Overview ==

NISC is a statically-scheduled horizontal nanocoded architecture (SSHNA). The term "statically scheduled" means that the [[operation scheduling]] and [[hazard handling]] are done by a [[compiler]]. The term "horizontal nanocoded" means that NISC does not have any predefined [[instruction set]] or [[microcode]]. The compiler generates nanocodes which directly control [[functional unitsunit]]s, registers[[Processor register|register]]s and multiplexers[[multiplexer]]s of a given [[datapath]]. Giving low-level control to the compiler enables better utilization of datapath resources, which ultimately result in better performance. The benefits of NISC technology are:

#* Simpler controller: no hardware scheduler, no instruction decoder

#* Better performance: more flexible architecture, better resource utilization

#* Easier to design: no need for designing instruction-sets

Instruction-The instruction set and controller of processors[[Central processing unit|processor]]s are the most tedious and time-consuming parts to design. By eliminating these two, design of custom processing elements become significantly easier.

Furthermore, the datapath of NISC processors can even be generated automatically for a given application. Therefore, designersdesigner's productivity is improved significantly.<br />

Since NISC datapaths are very efficient and can be generated automatically, NISC technology is comparable to [[High-level synthesis|high level synthesis]] (HLS) or [[C to HDL]] synthesis approaches. In fact, one of the benefits of this architecture style is its capability to bridge these two technologies (custom processor design and HLS).

== History ==