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→Architecture: Expanded section to explain register encoding. |
→Instruction encoding: Corrected significance in base-3 encoding of operands. |
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The encoding of the 3-operand register opcodes is quite unusual, since the number of registers is 3×4 and not a power of 2. The encoding used fits 0 to 3 operands, and the number of operands, into 11 bits. Thus, each opcode can be assigned four times, once to a 3-operand instruction, once to a 2-operand, etc.
The 3-operand form takes the low 2 bits of each register specifier and places each into a 2-bit field, using 6 bits. The high 2 bits of each operand are combined in base-3 into a number between 0 and 26 (using 9×''a''+3×''b''+
The 2-operand form uses the unused 5 combinations (27–31) in the 5-bit field. The 2-bit field for the low bits of operand ''a'' is reassigned; one bit is used for an additional opcode bit, and the other is used as an additional combination register specifier, allowing 10 combinations (54–63). 9 of those are assigned to encode the high bits of 2 operands (using 3×''b''+
1-operand instructions use the tenth combination value 63, and place the register number in the 4 available bits. (Only operand ''c'' is specified, and the high bits are stored in the ''b'' field.)
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