XCore Architecture: Difference between revisions

Revision as of 04:14, 6 January 2013

Revision as of 05:11, 6 January 2013

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Instructions can use between zero and six operands. Most common arithmetic operations (such as ADD, SUB, MULT) are [[Instruction_set#Number_of_operands|three-operand instructions]] based on a set of 12 general purpose registers.

{|class="wikitable" style="text-align:center"

Most instructions are 16 bits long and come in three forms:

|+XMOS instruction formats

# 5 bits of opcode, and up to 3 register operands specified in 11 bits, or

! 1<br/>5 || 1<br/>4 || 1<br/>3 || 1<br/>2 || 1<br/>1 || 1<br/>0 || <br/>9 || <br/>8 || <br/>7 || <br/>6 || <br/>5 || <br/>4 || <br/>3 || <br/>2 || <br/>1 || <br/>0 || Description

# 6 bits of opcode, one register specifier (4 bits) and a 6-bit unsigned immediate constant, or

|-

# 6 bits of opcode, and 10 bits of unsigned immediate constant.

|colspan=6| opcode ||colspan=10| immediate ||align=left| 10/20-bit immediate

|-

|colspan=6| opcode ||colspan=4| register ||colspan=6| immediate ||align=left| register & 6/16-bit immediate

|-

|colspan=6| opcode ||colspan=2| 1 1 ||colspan=2| opc ||colspan=6| immediate ||align=left| 6/16-bit immediate

|-

|colspan=5| opcode ||colspan=5| 9×''a''+3×''b''+''c'' ||colspan=2| a a ||colspan=2| b b ||colspan=2| c c ||align=left| 3-operand register

|-

|colspan=5| opcode ||colspan=6| 3×''b''+''c''+54 || o ||colspan=2| b b ||colspan=2| c c ||align=left| 2-operand register

|-

|colspan=5| opcode ||colspan=6| 1 1 1 1 1 1 || o ||colspan=4| c c c c ||align=left| 1-operand register

|-

|colspan=5| opcode ||colspan=6| 1 1 1 1 1 1 || o ||colspan=2| 1 1 ||colspan=2| opc ||align=left| 0-operand

|}

The last four forms share the same opcode range, because the number of operands is determined by bits 5 through 10. The last 3 forms use bit 4 as an additional opcode bit. (And the last form uses bits 1 and 0 as well.)

In the second form, some instructions (loads and stores_ use all 4 bits to encode the register number, allowing access to r12–r15. Other instructions use(conditional thosebranches) encodingsdo fornot additionalallow instructionsregister withnumbers onlyabove one11, 6-bitinstead allowing the immediatethird operandform.

Because constants are always unsigned, many instructions come in add/subtract pairs, e.g. jump forward and backward.

Because constants are always unsigned, many instructions come in add/subtract pairs, e.g. jump forward and backward.

In the second form, some instructions use all 4 bits to encode the register number, allowing access to r12–r15. Other instructions use those encodings for additional instructions with only one, 6-bit immediate operand.

The form of an instruction is determined by its 4 most-significant bits:

* '''00__''': 3 register operands (8 opcodes)

* '''0100''': 3 register operands (2 opcodes)

* '''0101''': register + 6-bit immediate (4 opcodes, 16 registers allowed)

* '''0110''': register + 6-bit immediate (4 opcodes, 16 registers allowed)

* '''0111''': register + 6-bit immediate (4 opcodes, 12 registers allowed)

* '''10__''': 3 register operands (8 opcodes)

* '''1100''': 3 register operands (2 opcodes)

* '''1101''': 10-bit immediate (4 opcodes)

* '''1110''': 10-bit immediate (4 opcodes)

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** '''11111''': 3 additional operands, in addition to the operands of the following register instruction

The encoding of the 3-operand register opcodes is quite unusual, since the number of registers is 3×4 and not a power of 2. The encoding used fits 0 to 3 operands, and the number of operands, into 11 bits. Thus, each 5-bit opcode can be assigned four times, once to a 3-operand instruction, once to a 2-operand, etc.

The 3-operand form takes the low 2 bits of each register specifier and places each into a 2-bit field, using 6 bits. The high 2 bits of each operand are combined in base-3 into a number between 0 and 26 (using 9×''a''+3×''b''+''c'') and stored in the remaining 5 bits.

The 2-operand form uses the unused 5 combinations (27–31) in the 5-bit field. TheOperand ''a'' is not used, and the 2-bit field for theits low bits of operand ''a'' is reassigned; one bit is used for an additional opcode bit, and the other is used as an additional combination register specifier, allowingdoubling 10the number of available combinations to 10 (54–63). 9 of those are assigned to encode the high bits of 2 operands (using 3×''b''+''c''+54).

1-operand instructions use the tenth combination value 63, and place the register number in the 4 available bits. (Only operand ''c'' is specified, and the high bits are stored in the ''b'' field.)

Finally, the 1-operand encoding, with a register number 12 or more (the ''b'' field contains binary 11), is also used to encode 0-operand instructions. The two low-order bits of the ''c'' field are available for additional opcode bits (bringing the total to 8).