XCore Architecture: Difference between revisions

Revision as of 05:11, 6 January 2013

Revision as of 23:32, 6 January 2013

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|colspan=5| opcode ||colspan=5| 9×''a''+3×''b''+''c'' ||colspan=2| a a ||colspan=2| b b ||colspan=2| c c ||align=left| 3-operand register

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|colspan=5| opcode ||colspan=65| 27+3×''b''+''c''+54 || * || o ||colspan=2| b b ||colspan=2| c c ||align=left| 2-operand register

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|colspan=5| opcode ||colspan=6| 1 1 1 1 1 1 || o ||colspan=4| c c c c ||align=left| 1-operand register

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The 3-operand form takes the low 2 bits of each register specifier and places each into a 2-bit field, using 6 bits. The high 2 bits of each operand are combined in base-3 into a number between 0 and 26 (using 9×''a''+3×''b''+''c'') and stored in the remaining 5 bits.

The 2-operand form uses the unused 5 combinations (27–31) in the 5-bit field. Operand ''a'' is not used, and the 2-bit field for its low bits is reassigned; one bit is used for an additional opcode bit, and the other is used as an additional combination register specifier, doubling the number of available combinations to 10, (54–63).and allowing all 9 combinations of those3×''b''+''c'' areto be represented. This is done in a manner assignedsimilar to encode[[bi-quinary coded decimal]]: the highcombination, bitsmodulo of5, is stored in the 25-bit operandsfield (usingas (3×''b''+''c'')&nbsp;mod&nbsp;5 +54 27), and the 1-bit quotient (⌊(3×''b''+''c'')/5⌋) is stored in instruction bit 5 (marked with an asterisk in the table above).<ref>The architecture manual documents bit 5 as the "most significant bit", but fails to mention the non-binary base; some [http://git.infradead.org/users/segher/dis-xs1.git/blob/HEAD:/dis-xs1.fs XS-1 disassembler source code] makes it clear. In the definition of <code>parse-inssn-r2</code>, the <code>1 #split 1b - swap 5 * +</code> portion splits the 6-bit register field into a 5-bit and a 1-bit part, subtracts 17 (hex 1b) from the high part, multiplies the low part by 5, and adds them.</ref>

1-operand instructions use the tenth combination value, 63with all 6 bits set, and place the register number in the 4 available bits. Only operand ''c'' is specified, and the high bits are stored in the ''b'' field.

Finally, the 1-operand encoding, with a register number 12 or more (the ''b'' field contains binary 11), is also used to encode 0-operand instructions. The two low-order bits of the ''c'' field are available for additional opcode bits (bringing the total to 8).

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Less frequently used instructions are encoded in 32 bits. These32-bit instructions encodeallow instructions16-or that operate on long20-bit immediate operands (such as far branches), onup ato large6 number ofregister operands (for example long multiply which has 4 source and two destination operands) and some instructions that are simply rarely used with fewer operands.

One 10-bit immediate opcode (PFIX, opcode 111100) is used to add an additional 10 bits to the 6- or 10-bit immediate in the following instruction.

One 3-operand opcode (EOPR, opcode 11111) is reserved for an "additional operands" prefix. Its 3 operands are used along with those of the following instruction word to produce additional 32-bit instructions with up to 6 operands. (2-operandThis 32-bit instructionsis also exist;used thosefor userarely-used a3- and 2-operand forminstructions; ofin EOPRsuch followedcases bythe following instruction word is a 0-operand instruction. The(In the 2-operand case, the extra opcode bit in the leading EOPR ''is'' used.)

==Sequential programming model==