XCore Architecture: Difference between revisions

Revision as of 23:32, 6 January 2013

Revision as of 23:47, 6 January 2013

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The last four forms share the same opcode range, because the number of operands is determined by bits 5 through 10. The last 3 forms use bit 4 as an additional opcode bit. (And the last form uses bits 1 and 0 as well.)

In the second form, some instructions (loads and stores_stores) use all 4 bits to encode the register number, allowing access to r12–r15. Other instructions (conditional branches) do not allow register numbers above 11, instead allowing the third form to share the opcode range.

Because constants are always unsigned, many instructions come in add/subtract pairs, e.g. jump forward and backward.

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** '''11111''': 3 additional operands, in addition to the operands of the following register instruction

The encoding of the 3-operand register opcodes is quite unusual, since the number of12 registers is 3×4 and not a power of 2. The encoding used fits 0 to 3 operands, and the number of operands, into 11 bits. Thus, each 5-bit opcode can be assigned four times, once to a 3-operand instruction, once to a 2-operand, etc.

TheIn 3-operandall form takescases, the low 2 bits of eachthe register specifiernumber andare placesplaced each intoin a 2-bit field, usingreducing 6the bits.problem to Theencoding the high 2 bits, of each operandwhich are combined in base-3the intorange a number betweenof 0 andto 26 (using 9×''a''+3×''b''+''c'') and stored in the remaining 5 bits2.

The 3-operand form places the low register numbers in the low 6 instruction bits. The high 2 bits of each register number are combined in base-3 into a number between 0 and 26 (using 9×''a''+3×''b''+''c'') and stored in the remaining 5 bits.

The 2-operand form uses the unused 5 combinations (27–31) in the 5-bit field. Operand ''a'' is not used, and the 2-bit field for its low bits is reassigned; one bit is used for an additional opcode bit, and the other is used as an additional combination register specifier, doubling the number of available combinations to 10, and allowing all 9 combinations of 3×''b''+''c'' to be represented. This is done in a manner similar to [[bi-quinary coded decimal]]: the combination, modulo 5, is stored in the 5-bit field (as (3×''b''+''c'')&nbsp;mod&nbsp;5 + 27), and the 1-bit quotient (⌊(3×''b''+''c'')/5⌋) is stored in instruction bit 5 (marked with an asterisk in the table above).<ref>The architecture manual documents bit 5 as the "most significant bit", but fails to mention the non-binary base; some [http://git.infradead.org/users/segher/dis-xs1.git/blob/HEAD:/dis-xs1.fs XS-1 disassembler source code] makes it clear. In the definition of <code>parse-inssn-r2</code>, the <code>1 #split 1b - swap 5 * +</code> portion splits the 6-bit register field into a 5-bit and a 1-bit part, subtracts 17 (hex 1b) from the high part, multiplies the low part by 5, and adds them.</ref>

The 2-operand form uses the unused 5 combinations (27–31) in the 5-bit field. Operand ''a'' is not used, and the 2-bit field for its low bits is reassigned; one bit is used for an additional opcode bit, and the other is used as an additional combination register specifier, doubling the number of available combinations to 10, and allowing all 9 combinations of 3×''b''+''c'' to be represented. This is done in a manner similar to [[bi-quinary coded decimal]]: the combination, modulo 5, is stored in the 5-bit field (as (3×''b''+''c'')&nbsp;mod&nbsp;5 + 27), and the 1-bit quotient (⌊(3×''b''+''c'')/5⌋) is stored in instruction bit 5 (marked with an asterisk in the table above).<ref>The architecture manual documents bit 5 as the "most significant bit", but fails to mention the non-binary base; some [http://git.infradead.org/users/segher/dis-xs1.git/blob/HEAD:/dis-xs1.fs XS-1 disassembler source code] makes it clear. In the definition of <code>parse-inssn-r2</code>, the <code>1 #split 1b - swap 5 * +</code> portion splits the 6-bit register field into a 5-bit and a 1-bit part, subtracts 1727 (hex 1b) from the high part, multiplies the low part by 5, and adds them.</ref>

1-operand instructions use the tenth combination value, with all 6 bits set, and place the register number in the 4 available bits. Only operand ''c'' is specified, and the high bits are stored in the ''b'' field.

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Finally, the 1-operand encoding, with a register number 12 or more (the ''b'' field contains binary 11), is also used to encode 0-operand instructions. The two low-order bits of the ''c'' field are available for additional opcode bits (bringing the total to 8).

(A few instructions use the operandregister number''c'' field value 0–11 as ana small immediate constant, or use it to select one of 12 convenient bit-shift

constants 0–8, 16, 24, or 32.)

Less frequently used instructions are encoded in 32 bits. 32-bit instructions allow 16-or 20-bit immediate operands (such as far branches), up to 6 register operands (for example long multiply which has 4 source and two destination operands) and someadditional instructionsopcode thatspace are simplyfor rarely used instructions.

One 10-bit immediate opcode (PFIX, opcode 111100) is used to add an additional 10 bits to the 6- or 10-bit immediate in the following instruction.

One 3-operand opcode (EOPR, opcode 11111) is reserved for an "additional operands" prefix. Its 3 operands are used along with those of the following instruction word to produce additional 32-bit instructions with up to 6 operands. This is also used for rarely-used 3- and 2-operand instructions; in such cases the EOPR specifies all 3 or 2 operands, and the following instruction word is a 0-operand instruction. (In the 2-operand case, the extra opcode bit in the leading EOPR ''is'' used.)

==Sequential programming model==